As the technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, it is difficult to achieve a stable threshold voltage for all CMOS semiconductor devices because atomic diffusion between adjacent gates causes shifts in the threshold voltage of CMOS semiconductor devices, thereby increasing the likelihood of device instability and/or device failure.
Accordingly, what is needed is a metal gate structure in which the threshold voltage is less sensitive to process variation.